Energy Power Efficient Vedic Multiplier Design on 28nm FPGA Using Vedic Formula ANURPYENA
نویسندگان
چکیده
منابع مشابه
Area Efficient Low Power Vedic Multiplier Design Using GDI Technique
Multipliers consume maximum amount of power during the partial product addition. For higher order multiplication, a huge number of adders are used to perform the partial product addition. Using compressor adders, that can add four, five , six or seven bits at a time, the number of full adders and half adders can be reduced and thus area and power consumed also gets reduced. These compressor add...
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ژورنال
عنوان ژورنال: Gyancity Journal of Engineering and Technology
سال: 2015
ISSN: 2456-0065
DOI: 10.21058/gjet.2015.1201